1. Field of the Invention
The present invention relates to a method and a device for synchronizing an image display.
2. Prior Art
In modern motor vehicles a requirement exists that image signals, which are provided by an external video source, should be displayed on an image display device (e.g. liquid crystal display) together with image signals generated locally in the image display device.
Typical applications for this are navigation displays that are displayed in the display of the combined instrument, together with other driving information, or in the center display. In the case of a failure of a head unit, a local display is additionally desired. A further application is rear-seat entertainment, that is to say display devices for the rear seats in which locally generated menus are displayed together with DVD contents supplied by a remotely arranged DVD player.
Various approaches are known for jointly displaying image signals that originate from different sources. The simplest approach operates unsynchronized. In this arrangement, a current image of a video source is continuously stored in a buffer memory and, at the same time, the image is read out and displayed together with locally generated data. The consequence of this is that normally disturbances occur in the display because no complete (consistent) images of the video source can be utilized. On the two sides of a separating line migrating through the image, parts of two successive frames of the video source are shown.
The most elaborate approach operates with a large RAM memory provided in the display device. In this memory, the current frame from the video source is in each case deposited usually in three buffer memories (triple buffering). In each case, the last frame completely acquired in the RAM memory is displayed. The advantage of this approach is the freedom from interference and the protection against failure—no synchronization is required. The disadvantage is the high memory requirement. Thus, about 2.3 MBytes of memory location are needed for a typical WVGA frame (800×480×16 bits/frame).
At various times, simple solutions were conceived in which a video sink in the display device is driven through the video source in slave mode. During this process, the timing of source and sink is “hard”, that is to say coupled by a common clock signal. The memory requirement is minimum, requiring, at the most, one FIFO of one line here. In the normal operating case, no disturbances occur. The main disadvantage is a lack of failure protection and especially the problems of start-up. This is because, as soon as the source is available again after a failure, it is necessary to switch “hard” from free-running to the timing of the source. This results in a disturbance which is visible on the display.
All the approaches described, are technically not very suitable, or uneconomic, especially for use in motor vehicles.
U.S. Pat. No. 7,030,934 B2 relates to a method for combining first and second video signals in a single display.
U.S. Pat. No. 5,923,377 A relates to a synchronization signal correction circuit that generates a corrected synchronization signal which is obtained by correcting a timing of a synchronization signal based on a time axis change component of the synchronization signal separated from an image signal. The corrected synchronization signal is used for initiating a change in a time axis error of the image signal.
US 2007/0038989 A1 relates to a display server which displays a first display frame during a first period and a second display frame during a second period.